Negative capacitance enables GAA scaling VDD to 0.5 V

A comprehensive study of the scaling negative capacitance FinFET (NC-FinFET) is conducted with TCAD. We show that NC-FinFET can be scaled to "2.1nm node" and almost "1.5nm comes two nodes after industry "3nm node," which has 16nm Lg last node according International Roadmap for Devices Systems (IRDS). In addition, intervening nodes, meet IRDS Ion Ioff target at target-beating VDD. The benefits (NC) include improved subthreshold slope (SS), drain-induced barrier lowering (DIBL), Vt roll-off, transconductance over Id (Gm/Id), output conductance (Gd/Id), lower Further may achieved by improving matching between ferroelectric (FE) dielectric (DE).